aod4184/AOI4184 40v n-channel mosfet general description product summary v ds i d (at v gs =10v) 50a r ds(on) (at v gs =10v) < 8m r ds(on) (at v gs =4.5v) < 11m 100% uis tested 100% r g tested symbol v ds drain-source voltage 40 the aod4184/AOI4184 used advanced trench technology and design to provide excellent r ds(on) with low gate charge. with the excellent thermal resista nce of the dpak package, those devices are well suited for high current load applications. v maximum units parameter absolute maximum ratings t a =25c unless otherwise noted 40v g d s g g d d s s d top view bottom view to-251a ipak to252 dpak topview bottom view g d s d g d s v ds v gs i dm i as , i ar e as , e ar t j , t stg symbol t 10s steady-state steady-state r jc typ max t c =25c 2.3 25 t c =100c junction and storage temperature range -55 to 175 c thermal characteristics units maximum junction-to-ambient a c/w r ja 18 44 22 parameter v 20 gate-source voltage drain-source voltage 40 avalanche energy l=0.1mh c mj avalanche current c 9.5 a v a t a =25c i dsm a t a =70c 120 pulsed drain current c continuous drain current g i d 50 40 t c =25c t c =100c power dissipation b p d continuous drain current 61 12 35 w power dissipation a p dsm w t a =70c 50 1.5 t a =25c maximum junction-to-case c/w c/w maximum junction-to-ambient a d 2.4 55 3 rev.2. 0: july 2013 www.aosmd.com page 1 of 6 downloaded from: http:///
aod4184/AOI4184 symbol min typ max units bv dss 40 v v ds =40v, v gs =0v 1 t j =55c 5 i gss 100 na v gs(th) gate threshold voltage 1.7 2.2 2.6 v i d(on) 120 a 6.7 8 t j =125c 11 13 8.5 11 m g fs 37 s v sd 0.72 1 v i s 20 a c iss 1200 1500 1800 pf c oss 150 215 280 pf c rss 80 135 190 pf r g 2 3.5 5 q g (10v) 21 27.2 33 nc q g (4.5v) 10 13.6 16 nc q gs 4.5 nc q gd 6.4 nc t d(on) 6.4 ns t 17.2 ns output capacitance turn-on delaytime dynamic parameters turn-on rise time v gs =10v, v ds =20v, i d =20a gate source charge gate drain charge total gate charge i s =1a,v gs =0v v ds =5v, i d =20a switching parameters maximum body-diode continuous current input capacitance v gs =4.5v, i d =15a forward transconductance diode forward voltage v =10v, v =20v, r =1 , gate resistance v gs =0v, v ds =0v, f=1mhz total gate charge reverse transfer capacitance v gs =0v, v ds =20v, f=1mhz static drain-source on-resistance i dss a v ds =v gs i d =250 a v ds =0v, v gs =20v zero gate voltage drain current gate-body leakage current m on state drain current electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions drain-source breakdown voltage i d =250 a, v gs =0v v gs =10v, v ds =5v v gs =10v, i d =20a r ds(on) t r 17.2 ns t d(off) 29.6 ns t f 16.8 ns t rr 20 29 38 ns q rr 18 26 34 nc components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. turn-on rise time body diode reverse recovery charge i f =20a, di/dt=100a/ s turn-off delaytime i f =20a, di/dt=100a/ s v gs =10v, v ds =20v, r l =1 , r gen =3 turn-off fall time body diode reverse recovery time a. the value of r ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air environ ment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user's specific board design, and the maximu m temperature of 175 c may be used if the pcb allows it. b. the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and i s more useful in setting the upper dissipation limit for cases where additional heatsi nking is used. c. repetitive rating, pulse width limited by juncti on temperature t j(max) =175 c. ratings are based on low frequency and duty cycl es to keep initial t j =25 c. d. the r ja is the sum of the thermal impedence from junction t o case r jc and case to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-case t hermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of t j(max) =175 c. the soa curve provides a single pulse rating. g. the maximum current rating is package limited. h. these tests are performed with the device mounte d on 1 in 2 fr-4 board with 2oz. copper, in a still air environ ment with t a =25 c. rev.2. 0: july 2013 www.aosmd.com page 2 of 6 downloaded from: http:///
aod4184/AOI4184 typical electrical and thermal characteristics 17 52 10 0 18 0 20 40 60 80 100 2 2.5 3 3.5 4 4.5 i d (a) v gs (volts) figure 2: transfer characteristics (note e) 5 6 7 8 9 10 0 5 10 15 20 25 30 r ds(on) (m ? ) i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 -50 -25 0 25 50 75 100 125 150 175 normalized on-resistance temperature (c) figure 4: on-resistance vs. junction temperature (note e) v gs =4.5v i d =15a v gs =10v i d =20a 25 c 125 c v ds =5v v gs =4.5v v gs =10v 0 20 40 60 80 100 120 0 1 2 3 4 5 i d (a) v ds (volts) fig 1: on-region characteristics (note e) v gs =3v 3.5v 5v 10v 4v 40 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 1.0e+02 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i s (a) v sd (volts) figure 6: body- diode characteristics (note e) 25 c 125 c (note e) 5 10 15 20 25 2 4 6 8 10 r ds(on) (m ? ) v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) i d =20a 25 c 125 c rev.2. 0: july 2013 www.aosmd.com page 3 of 6 downloaded from: http:///
aod4184/AOI4184 typical electrical and thermal characteristics 17 52 10 0 18 0 2 4 6 8 10 0 5 10 15 20 25 30 v gs (volts) q g (nc) figure 7: gate-charge characteristics 0 500 1000 1500 2000 2500 0 10 20 30 40 capacitance (pf) v ds (volts) figure 8: capacitance characteristics c iss 0 200 400 600 800 1000 0.00001 0.0001 0.001 0.01 0.1 1 10 power (w) pulse width (s) figure 10: single pulse power rating junction-to- c oss c rss v ds =20v i d =20a t j(max) =175 c t c =25 c 10 s 0.0 0.1 1.0 10.0 100.0 1000.0 0.01 0.1 1 10 100 i d (amps) v ds (volts) figure 9: maximum forward biased safe 10 s 10ms 1ms dc r ds(on) limited t j(max) =175 c t c =25 c 100 s 40 case (note f) 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 z ? jc normalized transient thermal resistance pulse width (s) figure 11: normalized maximum transient thermal imp edance (note f) single pulse d=t on /t t j,pk =t c +p dm .z jc .r jc t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse operating area (note f) r jc =3 c/w rev.2. 0: july 2013 www.aosmd.com page 4 of 6 downloaded from: http:///
aod4184/AOI4184 typical electrical and thermal characteristics 17 52 10 0 18 10 100 0.000001 0.00001 0.0001 0.001 i ar (a) peak avalanche current time in avalanche, t a (s) figure 12: single pulse avalanche capability (note c) 0 10 20 30 40 50 60 0 25 50 75 100 125 150 175 power dissipation (w) t case (c) figure 13: power de-rating (note f) 0 10 20 30 40 50 60 0 25 50 75 100 125 150 175 current rating i d (a) t case (c) figure 14: current de - rating (note f) t a =25 c 1 10 100 1000 0.001 0.1 10 1000 power (w) pulse width (s) figure 15: single pulse power rating junction - to - t a =25 c t a =150 c t a =100 c t a =125 c 40 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 z ? ja normalized transient thermal resistance pulse width (s) figure 16: normalized maximum transient thermal imp edance (note h) single pulse d=t on /t t j,pk =t a +p dm .z ja .r ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse figure 14: current de - rating (note f) figure 15: single pulse power rating junction - to - ambient (note h) r ja =55 c/w rev.2. 0: july 2013 www.aosmd.com page 5 of 6 downloaded from: http:///
aod4184/AOI4184 - + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms t t r d(on) t on t d(off) t f t off id + l vds bv unclamped inductive switching (uis) test circuit & waveforms vds dss 2 e = 1/2 li ar ar vdd vgs vgs rg dut - + vdc vgs id vgs i ig vgs - + vdc dut l vgs vds isd isd diode recovery test circuit & waveforms vds - vds + i f ar di/dt i rm rr vdd vdd q = - idt t rr rev.2. 0: july 2013 www.aosmd.com page 6 of 6 downloaded from: http:///
|
